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Computer Architecture (2015/2016)


Bachelor Informatica 2de jaar, Universiteit Leiden


Course objectives & learning topics

Develop qualitative and quantitative insight into the trade-offs of the major technological developments in computer architecture in the last twenty years.


Topics:

  • Instruction set architectures
  • Processors: pipelines, hazards, multiple issue and out-of-order execution
  • Memory: SRAM/DRAM tradeoffs, access times, hierarchy
  • Caches: associativity, indexing
  • Multi-cores & hardware multithreading
  • Vector processors & VLIW

IMPORTANT: to enroll in this year's labs, fill in the following questionnaire. It is mandatory to submit name and student ID, all other questions are optional.


Schedule

Location: Universiteit Leiden, Snellius Building. Lectures will be in room 174.

Lectures: See the LIACS Roosters


Contact & staff

Lecturer: Raphael 'kena' Poss; Lab Assistants: Kristian Rietveld, Mark Laagland.

In addition to the regular lab hours on Monday, every Thursday from 11.00 to 12.00h assistance will be available to answer questions about the lab assignments. Room: 411. (Note that Room 411 is not equipped with ULCN workstations, but web browser and ssh client are available, so you can only access your data of your ULCN account through ssh).

Assistance and course communication will take place on the mailing list liacs-ca-2015@googlegroups.com. You can subscribe to the group on this page, click the "subscribe to this group" link.

Additionally, assistance is available through IRC. This assistance is not available 24/7, but we try to answer questions on a best effort basis. We will use the freenode network and the #ca2015 channel. You can connect to irc.freenode.net using your favorite IRC client. (Note: within LIACS you might want to connect to port 8000 instead of the default 6667 which may be blocked). For more information see here.

One can also connect to the freenode network using a Web IRC client: https://webchat.freenode.net. As channel, fill in #ca2015.

IRC is not very suited for pasting long error reports from compilers, doing so "floods" everybody's screen with your compilation errors. If you need help with a compilation error, please first paste the output in "a pastebin": http://pastebin.com. After pasting your text and clicking "Submit", you will be redirected to a new temporary URL with a seemingly random name. Instead of pasting the long error report in the IRC window, paste this random URL instead and people can access your error report through that URL.


Evaluation

Weekly homework assignments: 20%
Lab assignments: 50%
Final exam: 30%
To pass the course you must obtain a passing grade separately for 1) homework + final exam and 2) lab work.


Tools

The software tools required for this course are C cross-compilers for Alpha and RISC-V, MGSim compiled for Alpha, and a working MGSim source tree to develop your own RISC-V ISA simulation. You can obtain these tools in either of two ways:



Course documents

(This section will be populated as the course moves forward)

General support documentation:

Course materials:
WeekLecture dateTopicHomeworkDeadline
1Aug 31st Introduction CA
To enroll in labs, fill in the questionnaire with at least your name and student ID.
2Sep 7th Performance, power, pipelines
1-3 Lab assignment 1 (intro assembly) + materials Sep 18th
3-4Sep 14th-21st Pipelines, latencies Week 3-4 Sep 25th
5Sep 28th S-RAM vs D-RAM, complexiteit, latencies
6Oct 5th Caching principles
7Oct 12th Caches, set-associative caches, LRU
4-8 Lab assignment 2 (ISA simulation) + materials Oct 23rd
9Oct 26th Part 1: I/O architectures and interrupt delivery
Part 2: Pipeline hazards (introduction)
10Nov 2nd Part 1: Scalar pipelines and intro to superscalar
Part 2: Instruction policies of out-of-order execution and new data hazards in superscalar pipelines
11Nov 9th Part 1: Instruction policies of out-of-order execution, mechanisms to avoid data hazards (cont.)
Part 2: Multi-core processors and explicit parallelism
9-11 Lab assignment 3 (optimization) + materials Nov 13th
12Nov 16th Virtual memory
13Nov 23rd Guest lecture on GPU computing by Ana Varbanescu. Main lecture slides, Additional slides on advanced CUDA concepts. Week 12-13 Nov 27th
14Nov 30th Summary and conclusions.
11-16 Lab assignment 4 (branch prediction) + materials Dec 18th

Article for week 12-13 homework: Cekleov, M. and Dubois, M., Virtual-address caches. Part 1: problems and solutions in uniprocessors. Only the first part is relevant for the assignment, but for interested readers the references cited in part 1 are listed at the end of part 2.

Article for lab assignment 4: Tse-Yu Yeh and Yale N. Patt.

Previous exams: see the web site of the Leidse Flesch.

Previous editions of this course:

2012, 2013, 2014