Computer Architecture (2014/2015)

Bachelor Informatica 2de jaar, Universiteit Leiden

Course objectives & learning topics

Develop qualitative and quantitative insight into the trade-offs of the major technological developments in computer architecture in the last twenty years.


  • Instruction set architectures
  • Processors: pipelines, hazards, multiple issue and out-of-order execution
  • Memory: SRAM/DRAM tradeoffs, access times, hierarchy
  • Caches: associativity, indexing
  • Multi-cores & hardware multithreading
  • Vector processors & VLIW


Location: Universiteit Leiden, Snellius

Lectures: See the LIACS Roosters

Extra werkcollege, preparation to exams: 14 january, room 402, 13:00-15:00.

Contact & staff

Lecturer: Raphael 'kena' Poss; Student assistants: Florian Treurniet, Rob Ooms, David van Es & Matthijs van Drunen.

Assistance and course communication will take place on the mailing list liacs-ca-2014@googlegroups.com. Please contact the assistants by e-mail to register to this list ASAP.


Weekly homework assignments: 20%
Lab assignments: 50%
Final exam: 30%
To pass the course you must obtain a passing grade separately for 1) homework + final exam and 2) lab work.


The software tools required for this course are C cross-compilers for Alpha and MIPS, MGSim compiled for Alpha, and a working MGSim source tree to develop your own MIPS ISA simulation. You can obtain these tools in either of three ways:

Course documents

(This section will be populated as the course moves forward)

General support documentation:

Course materials: ///
WeekLecture dateTopicHomeworkDeadline
1Sep 1st Introduction CA Sep 12th
2Sep 8th Performance, power, pipelines "Week 1-2" Sep 12th
3Sep 15th Termen, S-RAM vs D-RAM, latencies "Week 3-4" Sept 26th
4-6Sep 22nd-Oct 6th Caches, set-associative caches, LRU
7Oct 13th Virtual memory "Week 7-8", see below Oct 28th
9Oct 27th Part 1: I/O architectures and interrupt delivery
Part 2: Control hazards
Part 3: Data hazards (introduction)
11Nov 10th Part 1: Scalar pipelines and intro to superscalar
Part 2: Instruction policies of out-of-order execution and new data hazards in superscalar pipelines
13Nov 24th Part 1: Instruction policies of out-of-order execution, mechanisms to avoid data hazards
Part 2: Multi-core processors and explicit parallelism
14Dec 1st Summary and conclusions.
1-3 Lab assignment 1 (intro assembly) + materials Sep 19th
4-8 Lab assignment 2 (ISA simulation) + materials Oct 29th
9-12 Lab assignment 3 (branch predictor) + materials, see below for article Nov 19th
13-15 Lab assignment 4 (performance optimization) + materials Dec 17th

Article for week 7-8 homework: Cekleov, M. and Dubois, M., Virtual-address caches. Part 1: problems and solutions in uniprocessors. Only the first part is relevant for the assignment, but for interested readers the references cited in part 1 are listed at the end of part 2.

Article for lab assignment 3: Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history.

Previous exams: see the web site of the Leidse Flesch.

Previous editions of this course:

2012, 2013